1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device and a method for recovering a data write characteristics of the non-volatile semiconductor memory device. More specifically, the present invention relates to a non-volatile semiconductor memory device configured to store information in a floating gate, such as an EEPROM having a function of simultaneously erasing the memory cells as a whole, which is called a "flash memory", and a method for recovering a data write characteristics of the same non-volatile semiconductor memory device.
2. Description of Related Art
Referring to FIG. 1A, there is shown a layout patterm diagram of this type non-volatile semiconductor memory device, and referring to FIGS. 1B and 1C, there are shown sectional views taken along the line A--A in FIG. 1A.
As shown in FIG. 1A, in a memory array, a plurality of bit lines BL are, located to extend in parallel to each other, and a plurality of word lines WL are located to extend in parallel to each other and orthogonally to the bit lines BL. Under the word lines WL, a floating gate 3 is located, so that a memory cell MC is constituted at a position of the floating gate 3. In the memory cell MC, the word line WL constitutes a control gate 5. A source region 6 and a drain region 7 are formed in a P-type silicon substrate 1 so as to locate the control gate 5 between the source region 6 and the drain region 7. The source region 6 is formed to continue along the word line WL so that the source region 6 is in common to a plurality of memory cells. The drain region 7 is connected to the bit line BL through a contact hole 8.
As shown in FIG. 1B, the floating gate 3 is formed on a thin tunnel gate oxide film 3 formed on the P-type silicon substrate 1. On the floating gate 3, a gate insulator film 4 is formed, and the above mentioned control gate 5 is formed on the gate insulator film 4. As mentioned above, the control gate 5 is formed of a portion of the word line WL. In other words, the control gate 5 is formed integrally with the word line WL. At each side of the stacked structure of the floating gate 3 and the control gate 5, the source region 6 and the drain region 7 are formed in a surface of the silicon substrate 1 in a self-alignment manner.
This non-volatile semiconductor memory operation as a flash memory as mentioned below, with reference to FIGS. 1B and 1C illustrating a write operation and an erase operation, respectively.
For the writing, the source region 6 is connected to ground (0 V), and a high voltage of 12 V and a voltage supply voltage of 5 V are applied to the control gate 5 and the drain region 7 for about 10 .mu.s (microsecond), respectively. As a result, as shown in FIG. 1B, hot electrons are generated in a channel region between the source region 6 and the drain region 7 and under the control gate 5. Some of the generated hot electrons are injected into the floating gate 3 through the tunnel gate oxide film 2. Thus, the writing is executed. In a written memory cell, a threshold as a MOS transistor increases.
On the other hand, for reading, the source region 6 is connected to ground (0 V), and 5 V and 1 V are applied to the control gate 5 and the drain region 7, in order to detect whether or not a current flows through the memory cell. Under this bias condition, no current flows through the written memory cell, but a current flows through an erased memory cell.
For erase, 0 V and a high voltage of 10 V are applied to the control gate 5 and the source region 6, respectively, so that, due to a F-N (Fowler-Nordheim) tunnel phenomenon between the floating gate and the source region, electrons accumulated in the floating gate 3 are extracted through the tunnel gate oxide film 2 to the source region 2, as shown in FIG. 1C.
One of important problems currently encountered in this type of non-volatile semiconductor memory device, is deterioration of a write characteristics and an erase characteristics caused by repetition of the write and erase.
More specifically, the deterioration of the write characteristics and the erase characteristics caused by repetition of data write/erase is that, as shown in FIG. 2, the elevation of the threshold by the writing becomes small and the drop of the threshold by the erase becomes small. In particular, the writing characteristics deteriorates with a relative small number of write/erase repetitions so that it becomes impossible to elevate the "threshold after write" to a lower limit of a write level (a lower limit of a level permitting to recognize that the memory cell is in a written condition). The deterioration of the write characteristics restricts the data rewrite number (the number of write/erase operations) in the non-volatile semiconductor memory device.
The following is a reason about why the writing characteristics deteriorates.
In the writing operation, hot electrons generated by causing the drain current to flow, are injected into the floating gate 3 through the tunnel gate oxide film 2 in the proximity of the drain region 7, under influence of the high voltage applied to the control gate 5. In this process, a portion of the injected electrons is trapped in the gate oxide film 2 when the injected electrons pass through the gate oxide film 2. Therefore, if the write/erase operation is repeated, the electrons trapped in the tunnel gate oxide film 2 in the proximity of the drain region 7, increases. As a result, the trapped electrons relaxes a vertical electric field created in the tunnel gate oxide film 2 by the positive voltage applied to the gate electrode 5 at the time of writing data. Because of this, a writing speed of the memory cell after the write/erase operation is repeated becomes lower than that of a new memory cell just after it has been manufactured. In addition, the "threshold after writing" cannot sufficiently elevate.
On the other hand, the deterioration of the erase characteristics is attributable to the fact that, when the electrons accumulated in the floating gate 3 are extracted to the source region 2, a high electric field occurs in a portion of the tunnel gate oxide film 2 in the proximity of the source region 6, and the tunnel gate oxide film 2 is deteriorated by this high electric field portion.
In order to overcome this problem, Japanese Patent Application Laid-open Publication JP-A-02-0284473 has proposed to relax concentration of an electric field in an end of the source region, by (1) rounding the shape of the end of the floating gate 3 opposing to the source region 6, and (2) forming a low impurity density region in the end of the source region 6 opposing to the floating gate 3.
However, since the approach disclosed in JP-A-02-0284473 does not improve the writing characteristics, it could not remarkably increase the re-write number of the memory.